FIG. 1 is a circuit diagram illustrating a related art sub-ADC (analog to digital converter). The sub-ADC is an essential building block in pipeline ADCs, since the flash type thereof is a good candidate for high speed applications. In FIG. 1, the MDAC 101 and the sub-ADC 103 take place of the traditional Sample/Track and Hold stage to save power. But the sampling skew between the MDAC 101 and the sub-ADC 103 becomes crucial in this case. To solve this issue, in a sampling period, the sampling capacitors C1-C4 in the MDAC 101 and the sub-ADC 103 will sample the input signal Sip, Sin at the same time, meanwhile, extra sampling capacitors C5, C6 in the sub-ADC 103 will sample the corresponding reference signals Sr1, Sr2, which can be constant voltages. And in the hold period, the two pairs of sampling capacitors C3-C6 in the sub-ADC 103 will shunt together such that the comparing module 105 can get the voltage difference between the input signals Sip, Sin and the reference signals Sr1, Sr2. But above operation will divide the voltage difference by 2 because the charge difference will be shared by two capacitors. Also, the sub ADC 103 needs more time to wait for the charge redistribution in two sampling capacitors.